1. Field of the Invention
The present invention relates to a semiconductor device having a gate embedding layer on the surface of a semiconductor substrate reducing the effective gate length and reducing the drain conductance (g.sub.ad), and a method of producing the same.
2. Description of the Related Art
It is necessary to decrease the capacitance between a gate and a source in order to improve the high-frequency characteristics of a semiconductor device, particularly to achieve a high gain, and one of effective means for this purpose is to reduce the gate length. For this reason, a semiconductor device disclosed in Japanese Laid-Open Patent Publication No.5-218100 using a T-shaped gate electrode has been suggested. However, reducing the gate length leads to an increase in the drain conductance, that in a high-output power device, in particular, may lower the efficiency. Accordingly, the conventional T-shaped gate electrode has been insufficient to reduce the drain conductance.
With this background, semiconductor devices comprising a gate electrode that has a gate embedding layer and extending portions have been studied. FIG. 6 is a longitudinal sectional view of a semiconductor device showing an example. Reference numeral 30 denotes a semiconductor substrate that consists of a semi-insulating GaAs substrate 31, an n-GaAs active layer 32, a gate embedding layer 33 comprising an n-GaAs layer and a n.sup.+ -GaAs layer 34. Numeral 37 denotes a drain electrode made of an AuGe-based metal, 38 denotes a source electrode made of an AuGe-based metal, 40 denotes a gate electrode made of an Al-based metal, 40a denotes an embedded portion of the source electrode 40, and 40b, 40c denote extending portions of the gate electrode 40 that is joined with the gate embedding layer 33. The extending portions 40b, 40c extend laterally outwardly in opposite directions.
As shown in FIG. 6, it is made possible to reduce the effective gate length by embedding a central portion of the bottom of the gate electrode in the gate embedding layer 33 and reducing the width of the embedded portion 40a that is nearest to a channel. Also because the extending portions 40b, 40c on both sides (drain electrode and source electrode) of the embedded portion 40a are joined with the gate embedding layer 33, drain conductance can be reduced particularly when the value of drain voltage (VD) is increased, compared to a structure without extending portions on both sides.
FIGS. 7A-7D show a schematic flow sheet showing a conventional method of producing the semiconductor device shown in FIG. 6. As shown in FIG. 7A, a dummy gate electrode 35 made of photoresist applied to form the embedded portion 40a is formed on the n.sup.+ -GaAs layer 34 in first photolithography step. This is followed by the deposition of an insulation layer 36 made of SiO.sub.2 of a predetermined thickness, on the dummy gate electrode 35 and the n.sup.+ -GaAs layer 34, as shown in FIG. 7B. Then as shown in FIG. 7C, the n.sup.+ -GaAs layer 34 is etched through till the gate embedding layer 33 is exposed, thereby to form an opening in the n.sup.+ -GaAs layer 34. Formed thereafter are the drain electrode 37, the source electrode 38, and photoresist 39 applied to form the extending portions 40b, 40c in second photolithography step. Then as shown in FIG. 7D, etching is done so as to penetrate through the gate embedding layer 33 and increase the width of the opening. Thus a metal layer to form the gate electrode is deposited, and the gate electrode 40 having the embedded portion 40a and the extending portions 40b, 40c is formed, as shown in FIG. 7E.
In the conventional method, however, the embedded portion 40a and the extending portions 40b, 40c of the gate electrode 40 are formed in separate photolithography steps, and therefore misalignment during the photolithography step causes the extending portions 40b, 40c to be formed unsymmetrically with respect to the embedded portion 40a.
In a high output power device, as it ordinarily employs a multi-finger pattern for power output, in case the extending portions 40b, 40c are formed unsymmetrically with respect to the embedded portion 40a, there has been such a problem that fingers that are offset toward the drain electrode and fingers that are offset toward the source electrode are formed alternately, thus making causes for uneven operation or lower performance.